Field Oriented Control (FOC) is a motor control technique that has gained popularity in recent years, particularly in the control of Brushless DC (BLDC) motors. BLDC motors are known for their high efficiency, low maintenance requirements, and excellent dynamic response. However, they can be challenging to control due to their non-linear characteristics, which can lead to unpredictable performance and even damage to the motor.
FOC offers several advantages over other control techniques, particularly in terms of accuracy and efficiency. By controlling the motor in a coordinate system that separates the magnetic flux from the torque, FOC is able to precisely control both the motor speed and torque. This results in a smoother, more efficient operation of the motor, with reduced noise and vibration.
In addition, FOC allows for greater flexibility in the control of the motor. By adjusting the phase currents and the rotor position, FOC can achieve a wide range of operating characteristics, such as high starting torque and high-speed performance.
Overall, the advantages of FOC make it an increasingly popular choice for the control of BLDC motors, particularly in applications where high performance and reliability are essential.
Implementing FOC on a Field Programmable Gate Array (FPGA) offers several advantages, such as real-time processing, low latency, and scalability. The objective of this thesis is to design and implement a FOC algorithm for motor control on an FPGA, using hardware description languages (HDL) and digital signal processing (DSP) techniques. The proposed system will be tested and validated using a Brushless DC (BLDC) motor
The results of this thesis will demonstrate the feasibility and effectiveness of using FOC on an FPGA for motor control, and provide insights into the optimization and enhancement of the proposed system. This research will contribute to the development of high-performance, low-cost, and adaptable motor control solutions for various industrial, automotive, and robotics applications.
As we have a digital flow at MinDCet, the possibility exists to generate a real IC layout of the implemented HDL, to assess the impact of the design complexity on silicon area.